1. Field of the Invention
The present invention relates to a data generation method and circuit, and in particular to a generation method and circuit of data used for a 64B/66B encoding circuit.
2. Description of the Related Art
A data generation technology for 64B/66B encoding is applied to various places as shown by hatching in FIG. 5, i.e., an optical interface 10 within a transmission device 1 and a backboard transmitter 20 within a relay device 2 in a network which performs 64B/66B encoding to packet data like an Ethernet (registered trademark) packet, an IP packet, and the like to be transmitted.
Hereinafter, a prior art example of the data generation technology for 64B/66B encoding will be described referring to FIGS. 6, 7A, 7B, and 8.
Prior Art Example: FIGS. 6, 7A, 7B, and 8
In the prior art transmission device 1 shown in FIG. 6, a transmission processor 100 composing the optical interface 10 firstly receives packet data PD from the outside of the transmission device 1, and extracts the packet data PD, and its head and tail information SI and TI to be provided to an internal 64B/66B encoding data generation circuit 1000.
The 64B/66B encoding data generation circuit 1000 having received the data and the information sequentially generates user data UD by 64 bits (8 bytes) from the packet data PD, and 8-bit (1-byte) control data CD corresponding to each of the user data UD, and provides the generated data to a 64B/66B encoding circuit 200, thereby making the encoding circuit 200 perform encoding.
The 64B/66B encoding rule prescribes that the patterns of the user data UD and the control data CD to be provided to the 64B/66B encoding circuit 200 assume, as shown in the following, any one of patterns PTN1-PTN12 shown in FIG. 7A according to states of (1) an idle period when no packet data PD is received, (2) a start of a packet data PD reception, (3) the packet data PD reception, and (4) an end of the packet data PD reception.
Namely, a table in FIG. 7A shows 12 patterns PTN1-PTN12 of conversion relationships from the user data UD and the control data CD before encoding into encoded data ED after encoding. The 64B/66B encoding data generation circuit 1000 generates the user data UD and the control data CD corresponding to any of the patterns PTN1-PTN12, thereby enabling the 64B/66B encoding circuit 200 to generate the encoded data ED corresponding to the patterns PTN1-PTN12 as will be described in the following.
Also, as seen from FIG. 7A, idle bytes C0-C7 before encoding are respectively composed of 8 bits, while the idle bytes C0-C7 after encoding are respectively composed of 7 bits.
Also, the specification of the 64B/66B encoding rule is formed based on 4-byte data, which is referred to as 4 lanes. In the specification, the head of the data is located at the head of the 4 lanes. Therefore, the head position upon converting 4-byte data into 8-byte data is the 5th (pattern PTN2) or the 1st byte (pattern PTN3) within the 8 bytes.
(1) During Idle Period (Pattern PTN1)
During the idle period, the 64B/66B encoding data generation circuit 1000 generates, as shown in the pattern PTN1, the user data UD in which the idle bytes C0-C7 for 8 bytes are set and the control data CD (“11111111”) indicating that only the idle bytes C are set therein.
(2) Upon Start of Packet Data Reception (Pattern PTN2 or PTN3)
When receiving the head information SI of the packet data PD, the 64B/66B encoding data generation circuit 1000 generates the user data UD and the control data CD of the pattern PTN2 or the pattern PTN3 described hereinbelow according to phase conditions of a generation timing of the user data UD and a transition timing to the start of the packet data reception from the idle period.
When the idle period transitions to the start of the packet data reception during the generation of the user data UD, the 64B/66B encoding data generation circuit 1000 generates the user data UD in which the idle bytes C0-C3 for 4 bytes, a head identifying byte S4 of the packet data PD, data bytes D5-D7 for 3 bytes from the head of the packet data PD shown in the pattern PTN2 are set, and the control data CD (“11111000”) indicating the positions of the idle bytes C0-C3 and the head identifying byte S4 within the user data UD.
When the generation timing of the user data UD arrives immediately after the start of the packet data reception, the 64B/66B encoding data generation circuit 1000 generates the user data UD in which a head identifying byte S0 of the packet data PD, data bytes D1-D7 for 7 bytes from the head of the packet data PD shown in the pattern PTN3 are set, and the control data CD (“10000000”) indicating the position of the head identifying byte S0 within the user data UD.
(3) During Packet Data Reception (Pattern PTN4)
The 64B/66B encoding data generation circuit 1000 generates, as shown in the pattern PTN4, the user data UD in which the data bytes D0-D7 for 8 bytes are sequentially set from the packet data PD continuously received, and the control data CD (“00000000”) indicating that none of the idle byte C, head identifying byte S, and tail identifying byte T which will be described later is set in the user data UD.
(4) Upon End of Packet Data Reception (Patterns PTN5-PTN12)
When receiving tail information TI of the packet data PD, the 64B/66B encoding data generation circuit 1000 generates, according to a transfer status of the packet data PD as shown in the patterns PTN5-PTN12, user data UD in which tail identifying bytes T0-T7 are respectively added to a head or data bytes T0-T6 of a tail of the packet data PD, and idle bytes C for remaining bytes are further set, and the control data CD indicating the positions of the tail identifying bytes T0-T7 and the idle bytes C within the user data UD.
The 64B/66B encoding circuit 200 having received the user data UD and the control data CD generated as the above-mentioned (1)-(4) generates a parallel scrambled data SD of e.g. 16 bits in which encoding and scrambling based on the control data CD are applied to the user data UD, as shown in FIG. 6, and synchronizes the scrambled data SD with a clock CLK supplied from a P/S converter 30 to be outputted.
The 64B/66B encoding circuit 200 has, as shown in a general arrangement in FIG. 7B, a 64B/66B encoding processor 210 for encoding the user data UD and the control data CD to generate parallel encoded data ED of 66 bits, a FIFO buffer BUF for temporarily storing the encoded data ED, a scrambler 220 for reading the encoded data ED from the buffer BUF to generate scrambled data SD, a gear box 230 for performing a rate conversion to the scrambled data SD outputted from the scrambler 220 into parallel data of 64 bits, and a multiplexer 240 further multiplexing the scrambled data SD to which the rate conversion is performed by the gear box 230 and performing the rate conversion (4:1) into parallel data of 16 bits to be provided to the P/S converter 30.
Also, a clock CLK_IQ that is an internal clock CLK_I of the optical interface 10 supplied to the 64B/66B encoding data generation circuit 1000 and divided into four by a clock divider 250_1 is supplied to the 64B/66B encoding processor 210. It is to be noted that the clock division number “four” corresponds to a case where the packet data PD is supposed to be the parallel data of 16 bits as shown in FIG. 7B (namely, where the transmission rate of the user data UD (64 bits) is ¼ (= 16/64) times the transmission rate of the packet data PD (16 bits)), so that the clock division number of the clock divider 250_1 may be appropriately changed according to a parallel bit number of the packet data PD.
Also, a clock CLK_Q that is the clock CLK outputted by the P/S converter 30 divided into four by the clock divider 250_2 is supplied to the input side of the scrambler 220, the gear box 230, and the multiplexer 240, and the clock CLK is supplied to the output side of the multiplexer 240 as it is.
In operation, every time the user data UD and the control data CD generated by the 64B/66B encoding data generation circuit 1000 is received, the 64B/66B encoding processor 210 generates the encoded data ED according to the encoding rule shown in FIG. 7A from the user data UD and the control data CD, to be sequentially written in the FIFO buffer BUF.
The encoding data ED is data of 66 bits composed of a payload PL of 64 bits generated from the user data UD based on the control data CD, and a synchronous header HD of 2 bits added to the payload PL. In the synchronous header HD, “01” is set when the control data CD is “00000000” (in the case of pattern PTN1), and “10” is set in other cases (in the case of patterns PTN2-PTN12).
Also, the payload PL is set according to the patterns PTN1-PTN12 as follows:
Pattern PTN1
The 64B/66B encoding processor 210 sets in the payload PL a pattern identifying byte PI1 (0x1e) identifying the pattern PTN1, and the idle bytes C0-C7 respectively reduced to 7 bits.
Pattern PTN2
The 64B/66B encoding processor 210 sets in the payload PL a pattern identifying byte PI2 (0x33) identifying the pattern PTN2, the idle bytes C0-C3 respectively reduced to 7 bits, a padding PAD for 4 bits, and the data bytes D5-D7.
Pattern PTN3
The 64B/66B encoding processor 210 sets in the payload PL a pattern identifying byte PI3 (0x78) identifying the pattern PTN3, and the data bytes D1-D7.
Pattern PTN4
The 64B/66B encoding processor 210 sets in the payload PL the data bytes D0-D7 as they are.
Pattern PTN5
The 64B/66B encoding processor 210 sets in the payload PL a pattern identifying byte PI5 (0x87) identifying the pattern PTN5, a padding PAD for 7 bits, and the idle bytes C1-C7 respectively reduced to 7 bits.
Patterns PTN6-PTN11
The 64B/66B encoding processor 210 sets in the payload PL pattern identifying bytes PI6-PI11 (0x99, 0xaa, 0xb4, 0xcc, 0xd2, and 0xe1) respectively identifying the patterns PTN6-PTN11, the data bytes D0, D0-D1, D0-D2, D0-D3, D0-D4, and D0-D5, the idle bytes C1-C7, C2-C7, C3-C7, C4-C7, C5-C7, C6-C7, and C7 respectively reduced to 7 bits, and a padding PAD compensating lacking bits between the data byte D and the idle byte C.
Pattern PTN12
The 64B/66B encoding processor 210 sets in the payload PL a pattern identifying byte PI12 (0xff) identifying the pattern PTN12 and the data bytes D0-D6.
The scrambler 220 sequentially reads the encoded data ED from the FIFO buffer BUF, and provides to the gear box 230 the scrambled data SD that is the read encoded data ED to which the scrambling is applied. The gear box 230 provides the scrambled data SD sequentially received to the multiplexer 240 per 64 bits. The multiplexer 240 multiplexes the scrambled data SD into the parallel data of 16 bits to be provided to the P/S converter 30.
The P/S converter 30 having received the parallel data, as shown in FIG. 6, performs a serial conversion to the scrambled data SD to be transmitted to the network through the output port OP.
In the 64B/66B decoding, an S/P converter 40 having received the scrambled data SD through the input port IP generates (recovers) the clock CLK, and provides to a 64B/66B decoding circuit 300 the scrambled data SD to which a parallel conversion has been performed in synchronization with the clock CLK. The 64B/66B decoding circuit 300 having received the scrambled data SD provides to a reception processor 400 the user data UD and the control data CD obtained by descrambling and decoding the scrambled data SD. The reception processor 400 assembles the original packet data PD from the user data UD to be outputted to the outside.
Also, FIG. 8 shows a general arrangement of the relay device 2 shown in FIG. 5. In the relay device 2, S/P converters 40_1-40—n having received the scrambled data SD respectively through input ports IP1-IPn firstly provide the scrambled data SD to which the parallel conversion has been performed in synchronization with clocks CLK_1-CLK_n, in the same way as the 64B/66B decoding shown in FIG. 6, to 64B/66B decoding circuits 300_1-300—n composing the backboard transmitter 20. The 64B/66B decoding circuits 300_1-300—n respectively provide the user data UD and the control data CD obtained by descrambling and decoding the scrambled data SD to reception processors 400_1-400—n. 
The reception processors 400_1-400—n respectively provide the packet data PD assembled from the user data UD to a switch portion 500.
The switch portion 500 having received the packet data PD from any of the reception processors 400_1-400—n performs switching based on destination information or the like set in the header (not shown) of the packet data PD. The packet data PD and the head information SI and the tail information TI thereof are provided to any of the 64B/66B encoding data generation circuits 1000_1-1000—n. 
The 64B/66B encoding data generation circuits 1000_1-1000—n having received the data and the information respectively generate the user data UD and the control data CD from the packet data PD in the same way as the 64B/66B encoding data generation circuit 1000 within the transmission device 1 shown in FIG. 6 to be provided to 64B/66B encoding circuits 200_1-200—n. The 64B/66B encoding circuits 200_1-200—n respectively provide to P/S converters 30_1-30—n the scrambled data SD that is the user data UD to which encoding and scrambling have been performed. The P/S converters 30_1-30—n respectively perform the serial conversion to the scrambled data SD to be transmitted through output ports OP1-OPn.
It is to be noted that the following (1)-(3) can be mentioned as reference examples: